1. Field of the Invention
The present invention relates to a method and a circuit for interpolating an encoder output. In particular, the invention relates to a method and a circuit for interpolating an encoder output, by which two-phase sinusoidal signals output from an encoder are interpolated through sample-and-hold and A/D conversion, thereby outputting data in accordance with a data request signal from exterior, suited to encoder (photoelectric type, magnetic type, electromagnetic induction type, capacitance type, etc.) outputting two-phase sinusoidal signals having a phase difference of 90° and laser length measuring machines.
2. Description of the Related Art
Encoders have working limits on the pitches of their scale grids. In order to measure distances finer than the scale grids, it is therefore necessary to subdivide and interpolate the spatial periods of phase changes of the sinusoidal signals output from the encoders. Various types of interpolation circuits have been conventionally used for this purpose.
Among the conventional methods is one based on A/D conversion. Because of limited operation time for A/D conversion and signal correction, this method requires discrete sampling for the A/D conversion. If the sampling time is long, it is impossible to establish precise synchronization with external trigger signals (data request signals) such as an origin signal and a servo control signal, thereby causing a shift in position.
The applicant has proposed in Japanese Patent Laid-Open Publication No. Hei 10-132606 (hereinafter, patent document 1) that, as shown in FIG. 1 (corresponding to FIG. 1 of patent document 1), sample-and-hold (S/H) circuits 11a and 11b, A/D conversion circuits 12a and 12b, a look-up table (LUT) memory 13 for generating a phase angle tan−1 (B/A), and a register (REG) 14 of a phase angle conversion circuit 1 generate a phase angle PH (also denoted as θ) in accordance with the outputs INA and INB of encoders (not shown) at the timing of a first clock CK1. As shown in FIG. 2 (corresponding to FIG. 3 of patent document 1), the phase angle PH is linearly interpolated with a second clock CK2 which is faster than the first clock CK1 (eight times, in patent document 1), whereby two-phase square wave signals OUTA and OUTB (also denoted as QA and QB) are output for improved dynamic precision. In the diagram, the reference numeral 2 represents a data updating circuit which includes a subtractor 21, an absolute value unit 22, a polarity detection circuit 23, a limiter 24, a polarity addition circuit 25, an adder 26, and a register 27. The reference numeral 3 represents an integrating circuit which includes a register 31, an adder 32, and a register 33. The reference numeral 4 represents a carry detection circuit, and 5 a two-phase square wave generating circuit.
As shown in FIG. 3 (general block diagram) and FIG. 4 (timing chart), according to this interpolation circuit 42 shown in FIG. 1 of patent document 1, the output data D of an up/down counter 52 of a counter processing unit 50 for counting two-phase square waves can be latched by a latch circuit 54 even if a trigger signal TRG is input from exterior such as a touch probe 38. This makes it possible to maintain positioning in synchronization with TRG without impairing the dynamic precision. In FIG. 3, the reference numeral 44 represents an RS485 line driver, 46 a cable, and 48 an RS485 line receiver, for example.
There are problems, however, because (1) the enhanced number of interpolations increase the two-phase square waves in weight, so that the two-phase square waves become higher in frequency even at the same feed speed. (2) The period Pck1 of the first clock CK1 also increases to lower the dynamic precision. Description will be given below in detail.
(1) Increase in the output frequency of the two-phase square waves
For example, suppose that a feed speed v=1 m/s and a signal pitch λ=20 μm. If the number of interpolations Ni is increased from 200 to 2000, the resolution R improves from 0.1 μm to 0.01 μm. In the meantime, the edge interval Δt between the two-phase square waves decreases from 10 MHz (=1 m/s÷0.1 μm) to 100 MHz (=1 m/s÷0.01 μm).
This makes it impossible to use inexpensive transmission modes having transfer rates of around 10 to 40 MHz, such as RS422 and RS485.
One of the techniques for avoiding this is to integrate the function of the up/down counter 52 of the two-phase square waves into the interpolation circuit 42. This can surely avoid the data transmission problem of the two-phase square waves, whereas it becomes necessary to transmit data on the counter which includes a greater amount of information. Data transmission over a distance as long as several tens of meters in a parallel fashion may increase the cost and power consumption due to the large number of cable conductors. As described in Japanese Patent Laid-Open Publication No. 2000-33785 (hereinafter, patent document 2), a serial data transmission mode has thus been known.
This serial data transmission mode is commonly used for numerical control (NC) machines in particular. Signals synchronous with a data request signal RQ from an NC machine are output (DT), for example, in a start-stop manner. The output period is around 50 to 200 μs.
Here, in order to improve the positioning accuracy of the control machine, high dynamic precision is required of the position data with respect to RQ. This requires high-precision synchronization of the sampling time for the A/D conversion (ADC). For example, given a feed speed of 10 mm/s and a dynamic precision of 10 nm, a synchronization precision of 1 μs or below is required (10 mm/s÷10 nm=1 μs).
(2) Increase in the ADC sampling period Pck1
On the other hand, the ADC sampling period Pck1 is also limited. When the ADC bit length is increased for the sake of a greater number of interpolations, the A/D conversion time usually increases. Moreover, when the offsets and amplitude ratio of the two-phase sinusoidal waves are corrected to improve the interpolation precision as described in Japanese Patent Laid-Open Publication No. Hei 10-311741 (hereinafter, patent document 3), the sampling period Pck1 increases because of the operation time. As a result, the sampling period Pck1 sometimes becomes greater than synchronization errors. This requires some techniques for avoiding this and reducing synchronization errors.
Furthermore, the use of the ADC circuit having a greater number of bits for high resolution has also produced the problem of increased operation time.